With the recent trend for high-speed interfaces, the sensitivity of circuits towards process, voltage and temperature (PVT) variation is hampering both circuit performance and yields. For example, in the case of input/output (I/O) pads, it is difficult to meet the rise and fall times, current, power, and ground bounce specifications across all PVT corners. See Qadeer A. Khan, G. K. Siddhartha, Divya Tripathi, Sanjay Kumar Wadhwa, Kulbhushan Misri, “Techniques for on-chip process voltage and temperature detection and compensation,” in Proc. IEEE Int. Conference on VLSI Design (VLSID), p. 6, 2006. Driver circuits are oversized to meet timing at slow corners. This causes high current and simultaneous switching noise (SSN) at fast corners. Such effects degrade the reliability of the circuit and require considerable amount of design resources and time to meet circuit performance criteria across PVT variations. To overcome these problems, several inventions concerning PVT compensation may keep the output slew rates within a small range. See, e.g., Dong-Suk Shin, Inhwa Jung, Chulwoo Kim, Hyung-Dong Lee, and Young-Jung Choi, “Impedence-controlled pseudo-open drain output driver circuit and method for driving the same,” U.S. Pat. No. 7,579,861, Aug. 25, 2009; Mel Bazes, “Speed-locked loop to provide speed information based on die operating conditions,” U.S. Pat. No. 7,123,066, Oct. 17, 2006; Qadeer A. Khan, Sanjay K Wadhwa, Divya Tripathi, Siddhartha Gk, and Kulbhushan Misri, “PVT variation detection and compensation circuit,” U.S. Pat. No. 7,495,465, Feb. 24, 2009; the contents of all of which are incorporated herein by reference. These inventions, however, have not been applied in the area of mixed-voltage I/O circuits.
Accordingly, there is an immediate need for improved 2×VDD voltage tolerant logic, and in particular 2×VDD voltage tolerant I/O buffers with process, voltage and temperature (PVT) compensation.